The present invention relates to a semiconductor device having a plurality of transistors required to be isolated from each other on a silicon substrate and a method of manufacturing such a semiconductor device.
Nowadays, this type of semiconductor devices used for DRAMs tends to employ shallow trench isolation (STI) technology in order to isolate a plurality of transistors from each other, instead of local oxidation of silicon (LOCOS) technology. For example, Japanese laid-open patent publication No. 9-129721 (Patent Document 1) discloses a method of manufacturing a semiconductor device with STI technology.
Specifically, Patent Document 1 discloses a method of manufacturing a semiconductor device which can improve a difference in threshold voltage between the centers of active regions isolated by STI and corner portions of the active regions adjacent to the STI. However, Patent Document 1 fails to teach or suggest that a range in which a circuit area can be reduced has a limitation in a case where elements are insulated from each other by formation of trenches. Thus, with use of STI technology according to Patent Document 1, a degree of integration of elements is disadvantageously limited by the width and depth of trenches.
The aforementioned disadvantage will be described in greater detail with reference to a general manufacturing method of a semiconductor device which uses STI technology as shown in FIGS. 1 to 5.
First, an insulator film 11 is formed on a silicon substrate (e.g., a p-type silicon substrate) 10. An active region is covered with a photoresist (not shown). The insulator film 11 is dry-etched at a non-active region while the photoresist is used as a mask. Next, while the etched insulator film 11 is used as a mask, the silicon substrate 10 is dry-etched at the non-active region so as to form a trench 12 in the silicon substrate 10 (see FIG. 1).
Subsequently, in order to isolate elements, such as transistors, from each other, an insulator film 13 is deposited on the silicon substrate 10 and within the trench 12. Then chemical mechanical polishing (CMP) is performed on the insulator film 13. At that time, the insulator film 11 serves as a stopper for CMP. Next, the insulator films 13 and 11 are wet-etched in order to match the height of the insulator film 13 with a surface of the silicon substrate 10. As shown in FIG. 2, STI is formed so that the insulator film 13 remains within the trench 12. Thus, element formation regions isolated by the STI, i.e., active regions 141 and 142, are formed in the silicon substrate 10. Well isolation regions for electrical isolation from adjacent elements may be formed below the active regions 141 and 142 by implantation.
After the formation of the STI, a gate oxide film 15 is formed on the active regions 141 and 142 of the silicon substrate 10 by thermal oxidation or the like. Subsequently, a gate electrode 16 having a plurality of layers (three layers in FIG. 3) is formed on the gate oxide film 15. Furthermore, an insulator film 17 is deposited on the gate electrode 16. After that, while a photoresist is used as a mask, the gate electrode 16 and the insulator film 17 are dry-etched. Thus, as shown in FIG. 3, gates 18 and 19 including the gate oxide film 15 and the insulator film 17 are formed on the active regions 141 and 142 of the silicon substrate 10.
Next, an insulator film for formation of gate sidewalls is deposited and then dry-etched so as to form gate sidewalls 20. Furthermore, an insulator film for formation of a gate interlayer dielectric film is deposited on the silicon substrate 10. Then CMP is performed so as to form a gate interlayer dielectric film 21 (see FIG. 4).
Finally, while a photoresist is used as a mask, the insulator film 21 is dry-etched so as to form source/drain contacts for the transistors including the gates 18 and 19, respectively, at the active regions of the silicon substrate 10. Specifically, source/drain contacts 22 and 23 are formed for the gate 18 whereas source/drain contacts 24 and 25 are formed for the gate 19 (see FIG. 5).
FIG. 6 shows a two-dimensional arrangement of the semiconductor device shown in FIG. 5. FIG. 5 is a cross-sectional view taken along line A-A of FIG. 6. In FIG. 6, active regions 141 and 142 are arranged in a transverse direction (row direction) and a longitudinal direction (column direction). The active regions 141 and 142 arranged in the row direction and the column direction are insulated from each other by the insulator film 13 provided in the trench, i.e., the STI. The gates 18 and 19 are provided on the active regions 141 and 142, respectively. The common gate 18 is provided on the active regions 141 arranged in the column direction, and the common gate 18 is provided on the active regions 142 arranged in the column direction.
As shown in FIG. 6, portions around the active regions 141 and 142 are surrounded by the STI. Accordingly, in order to reduce a circuit area, it is necessary to reduce the size of the STI between the active regions, i.e., the size of the trench.
However, reduction of the size of the trench has limitations caused by formation of the trench, embedment of the insulator film 13 for isolation, and the like. Furthermore, reduction of the width and depth of the trench causes deterioration of insulating properties between elements.